1. Field of the Invention
This invention relates to integrated high level digital circuitry, precision analog circuitry, and power circuit structures on a monolithic semiconductor wafer, and more particularly to integrated circuitry and processes for realizing same, which result in cost effective high voltage, high power H-bridge or totem pole configurations, integrated along with precision analog circuitry and high density digital logic, and to circuitry incorporating such integrated circuitry which is particularly suitable for motor applications and the like.
2. Description of the Relevant Art
Many smart power integrated circuit applications require high voltage, high power H-bridge or totem pole configurations integrated along with precision analog circuitry and high density digital logic. This need is extremely prevalent in motor applications where cost is also of critical concern.
Although efforts have long been directed toward fully integrating high level digital circuitry, precision analog circuitry, and power circuit structures on a monolithic semiconductor wafer, success has not yet been achieved. Voltage breakdown considerations have generally forced power MOSFET approaches to be employed in lieu of bipolar implementations in order to avoid secondary breakdown effects. However, the breakdown voltage enhancement of MOSFET transistors is offset by the disadvantage of no conductivity modulation of the blocking region, which causes high ohmic drops in high voltage applications. Consequently, power MOSFET transistors require larger silicon area than bipolar transistors and have a reduced transconductance per unit area than bipolar transistors. Morever, the MOSFET transconductance is reduced at elevated temperatures due to mobility degradation. Furthermore, power MOSFET wafer fabrication is more complex than bipolar processing, and, as a result, power MOSFET devices are inherently more expensive than bipolar equivalents.
In addition to voltage breakdown considerations, power MOSFET devices have some other advantages over bipolar. Fast switching speeds without stored charge effects dramatically reduce power losses due to switching effects. Unlike bipolar devices, power MOSFETs have a high input impedance, although power MOSFETs also have a high input capacitance. Due to the input impedance and lack of stored charge, power MOSFET transistors offer simpler input drive techniques than bipolar transistors. In summary, power bipolar and power MOSFET transistors each have advantages and disadvantages.
Major voltage, charge, temperature, and electrical isolation problems exist in smart power integrations. The electrical isolation problem is due to the fact that power transistors are vertical current conductors with topside and backside power bus structures, while conventional integrated circuits employ lateral current conduction to some degree with the current conductors generally located on the wafer topside, and with the wafer backside reserved for component isolation. Thus, it is not possible to integrate, for instance, an H-bridge or totem pole circuit with conventional power transistors with electrical isolation. A true power implementation can be realized by a monolithic three-dimensional, non-planar wafer processing for which neither conventional bipolar or MOSFET power transistors are suitable.
Voltage isolation requires the ability to constrain high electric fields from one part of the die from influencing low voltage circuitry in the other part. Furthermore, it is difficult to prevent deleterious effects due to high electric fields on planar, oxide passivated wafers. The lack of charge isolation is due to long diffusion lengths associated with modern processing which allow parasitic charge injection from one part of the die to another resulting in deleterious circuit performance. The thermal coupling throughout the die tends to cause severe problems in the analog, and secondary problems in the digital circuitry, due to the heat generated in the power devices. Conventional wafer processing techniques do not lend themselves to proper electrical, voltage, charge, and thermal isolation to allow full smart power integration.
Merged technologies tend to increase process complexity and costs while reducing component performance. The high voltage devices dictate the non-compensated film characteristics. Low voltage devices are fabricated with whatever compromises are necessary to merge the components. Analog circuitry is best implemented by bipolar devices, normally employing inferior lateral PNP transistors in many circuit applications. Digital circuitry is often implemented by CMOS techniques which provide self-isolation at the expense of increased process complexity. CMOS implementations have the advantages of low power dissipation, high speed, and high packing density.